18.6 Cache Test Mode Protocol

Normal Read Protocol

A cache test mode normal read operation reads a selected RAM array. The read address, way, and array are specified by the read command.

The external agent issues a normal read command by:

 After a read latency of 15 PClk cycles, the processor provides the read response by:

 In the following SysClk cycle, the processor reverts to Slave state.

Normal reads have a repeat rate of 17 PClk cycles.

Figure 18-5 depicts two cache test mode normal reads.



Figure 18-5 Cache Test Mode Normal Read Protocol

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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